Media Partners and Other IEEE Conferences
Media Partners and Other IEEE Conferences
Media Partners and Other IEEE Conferences

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2018 Primer Course

Date: Monday, October 15, 2018
Time: 7:30 AM - 12:00 PM

Discussion Topic: SiGe Technology and mmW Layout Techniques


  • Pascal Chevalier (ST-Microelectronics)
  • Shahriar Shahramian (Bell Labs/Nokia)

7:00 - 7:50 AM   Registration and breakfast
7:50 - 8:00 AM Welcome Bruce Green and The’ Linh Nguyen

Course Overview
Renowned experts from industry teach present more tutorial and fundamental instruction for those new to the field or wanting a refresher. This will include SiGe technology and mm-wave layout tips and tricks components.

8:00 - 9:40 AM

Fundamentals of High-Speed SiGe BiCMOS Technologies

Instructor: Pascal Chevalier (STMicroelectronics)

Since the qualification in production of the first SiGe BiCMOS technology in a 0.5-µm CMOS node 20 years ago, many high-speed BiCMOS platforms were developed at different locations in various CMOS nodes, to reach today 55nm for the most advanced one. They remain appealing for many applications in spite of the growing attractiveness of CMOS technologies for RF applications during this period. The objective of this primer course is to understand fundamentals of high-speed SiGe BiCMOS technologies. The main focus will be on Si/SiGe Heterojunction Bipolar Transistor (HBT), but topics related to CMOS node and passive devices will be covered as well. The course will start with a review of the figures of merit and related extraction methods involved in SiGe HBT and BiCMOS technology. Advantages and positioning of BiCMOS compared to CMOS will also be shown. The second part will concentrate on high-speed SiGe HBT. Basics on device physics, related trade-offs and transistor architectures will be analyzed. Vertical and lateral scaling of the transistor will be discussed. This part will end with a presentation of SiGe HBT state-of-the-art and a review of different modeling tools used for the development of BiCMOS technologies. The third and last part will begin with a presentation of BiCMOS state-of-the-art. Bipolar / CMOS integration schemes will then be shown and related opportunities and challenges accompanying CMOS scaling will be examined. Fabrication of medium & high-voltage SiGe HBTs and passive devices, with in particular the impact of back-end of line, will also be discussed. The course will be illustrated with examples taken from 0.35-µm to 55-nm SiGe BiCMOS technologies developed by STMicroelectronics.

Pascal Chevalier received the Ph.D. degree in electronics from the University of Lille, France, in 1998 for his work on AlInAs/GaInAs InP-based HEMT. He has worked on BiCMOS technologies for nearly 20 years, starting from 0.35-µm Si BiCMOS at Alcatel Microelectronics, Belgium, to the most recent 55-nm SiGe BiCMOS at STMicroelectronics, France. He led research on advanced RF and millimeter-wave silicon-based devices such as SiGe HBT and Si LDMOS transistors for bulk and partially depleted SOI CMOS derivative technologies. He is currently managing the Mixed Signal (including RF-SOI CMOS) & BiCMOS Technologies R&D team at STMicroelectronics where he is also a Senior Member of the Technical Staff.

9:40 - 10:10 AM Break

10:10 - 11:50 AM
The Art of mm-Wave Layout

Instructor: Shahriar Shahramian (Bell Labs/Nokia)

We live in the golden age of mm-wave ASIC design! With the rise of 5G networks, a massive push for commercialization of mm-wave integrated circuits is underway. This course explores the hidden impairments which are often overlooked or difficult to locate in mm-wave layouts and interconnects. Using real-life fabricated circuit blocks operating in the W-Band and optical circuits operating beyond 100Gb/s, you are invited to search for parasitic capacitive, inductive, resistive and coupled elements which can adversely affect the circuit performance. After the modeling of these elements, simulations demonstrate the impact of the parasitics on bandwidth, center frequency, stability and noise-figure. Using simple and quick modeling techniques, the designers can incorporate various layout effects into their design. Finally, mm-wave techniques at chip level are explored from ground planes to packaging.

Shahriar Shahramian received his Ph.D. degree from University of Toronto in 2010 where he focused on the design of mm-wave data converters and transceivers. Dr. Shahramian has been with the Bell Laboratories division of Alcatel-Lucent (now Nokia), Murray Hill, NJ since 2009 and is currently the Director of the mm-Wave ASIC Research Department. He is also a member of the technical program committee of IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS) and IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). He is also a guest Editor of the IEEE Journal of Solid-State Circuits (JSSC). His research focus includes the design of mm-wave wireless and wireline integrated circuits. He is the lead designer of several state-of-the-art ASICs for optical coherent and wireless backhaul products at Bell Laboratories. Dr. Shahramian has been the recipient of Ontario Graduate Scholarship, University of Toronto Fellowship and the best paper award at the CSICS Symposium in 2005, 2015 and RFIC Symposium in 2015. He also holds an adjunct associate professor position at Columbia University, has received several teaching awards and is the founder and host of The Signal Path educational video series.

11:50 - 12:00 PM           Course Evaluation